cleanup: Re-run return_directly.cocci

Coccinelle's indentation of virt_create_plic() results in a long line.
Avoid that by mimicking the old indentation manually.

Don't touch tests/tcg/mips/user/.  I'm not sure these files are ours
to make style cleanups on.  They might be imported third-party code,
which we should leave as is to not complicate future updates.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250407082643.2310002-2-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Markus Armbruster 2025-04-07 10:26:41 +02:00
parent 91d0d16b44
commit 720a0e417e
10 changed files with 20 additions and 51 deletions

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@ -118,11 +118,8 @@ static void pca9554_write(PCA9554State *s, uint8_t reg, uint8_t data)
static uint8_t pca9554_recv(I2CSlave *i2c)
{
PCA9554State *s = PCA9554(i2c);
uint8_t ret;
ret = pca9554_read(s, s->pointer & 0x3);
return ret;
return pca9554_read(s, s->pointer & 0x3);
}
static int pca9554_send(I2CSlave *i2c, uint8_t data)

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@ -209,7 +209,6 @@ static int xen_xenstore_post_load(void *opaque, int ver)
{
XenXenstoreState *s = opaque;
GByteArray *save;
int ret;
/*
* As qemu/dom0, rebind to the guest's port. The Windows drivers may
@ -231,8 +230,7 @@ static int xen_xenstore_post_load(void *opaque, int ver)
s->impl_state = NULL;
s->impl_state_size = 0;
ret = xs_impl_deserialize(s->impl, save, xen_domid, fire_watch_cb, s);
return ret;
return xs_impl_deserialize(s->impl, save, xen_domid, fire_watch_cb, s);
}
static const VMStateDescription xen_xenstore_vmstate = {

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@ -1276,27 +1276,22 @@ static FWCfgState *create_fw_cfg(const MachineState *ms)
static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
int base_hartid, int hart_count)
{
DeviceState *ret;
g_autofree char *plic_hart_config = NULL;
/* Per-socket PLIC hart topology configuration string */
plic_hart_config = riscv_plic_hart_config_string(hart_count);
/* Per-socket PLIC */
ret = sifive_plic_create(
memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
plic_hart_config, hart_count, base_hartid,
VIRT_IRQCHIP_NUM_SOURCES,
((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
VIRT_PLIC_PRIORITY_BASE,
VIRT_PLIC_PENDING_BASE,
VIRT_PLIC_ENABLE_BASE,
VIRT_PLIC_ENABLE_STRIDE,
VIRT_PLIC_CONTEXT_BASE,
VIRT_PLIC_CONTEXT_STRIDE,
memmap[VIRT_PLIC].size);
return ret;
return sifive_plic_create(
memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
plic_hart_config, hart_count, base_hartid,
VIRT_IRQCHIP_NUM_SOURCES,
((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE,
VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE,
VIRT_PLIC_CONTEXT_BASE,
VIRT_PLIC_CONTEXT_STRIDE,
memmap[VIRT_PLIC].size);
}
static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,

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@ -242,10 +242,7 @@ static uint32_t esp_get_stc(ESPState *s)
static uint8_t esp_pdma_read(ESPState *s)
{
uint8_t val;
val = esp_fifo_pop(s);
return val;
return esp_fifo_pop(s);
}
static void esp_pdma_write(ESPState *s, uint8_t val)

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@ -110,8 +110,6 @@ static bool vfio_multiple_devices_migration_is_supported(void)
int vfio_block_multiple_devices_migration(VFIODevice *vbasedev, Error **errp)
{
int ret;
if (vfio_multiple_devices_migration_is_supported()) {
return 0;
}
@ -129,9 +127,8 @@ int vfio_block_multiple_devices_migration(VFIODevice *vbasedev, Error **errp)
error_setg(&multiple_devices_migration_blocker,
"Multiple VFIO devices migration is supported only if all of "
"them support P2P migration");
ret = migrate_add_blocker_normal(&multiple_devices_migration_blocker, errp);
return ret;
return migrate_add_blocker_normal(&multiple_devices_migration_blocker,
errp);
}
void vfio_unblock_multiple_devices_migration(void)

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@ -237,12 +237,10 @@ uint64_t qemu_plugin_tb_vaddr(const struct qemu_plugin_tb *tb)
struct qemu_plugin_insn *
qemu_plugin_tb_get_insn(const struct qemu_plugin_tb *tb, size_t idx)
{
struct qemu_plugin_insn *insn;
if (unlikely(idx >= tb->n)) {
return NULL;
}
insn = g_ptr_array_index(tb->insns, idx);
return insn;
return g_ptr_array_index(tb->insns, idx);
}
/*

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@ -364,8 +364,6 @@ static void test_watchdog_inten_luminary(const void *ptr)
int main(int argc, char **argv)
{
int r;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
@ -393,7 +391,5 @@ int main(int argc, char **argv)
test_watchdog_inten);
}
r = g_test_run();
return r;
return g_test_run();
}

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@ -191,12 +191,10 @@ static uint8_t pnv_i2c_pca9554_read_pins(PnvI2cDev *dev)
{
uint8_t send_buf[1];
uint8_t recv_buf[1];
uint8_t inputs;
send_buf[0] = PCA9554_INPUT;
pnv_i2c_send(dev, send_buf, 1);
pnv_i2c_recv(dev, recv_buf, 1);
inputs = recv_buf[0];
return inputs;
return recv_buf[0];
}
static void pnv_i2c_pca9554_flip_polarity(PnvI2cDev *dev)

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@ -360,8 +360,6 @@ static void test_clock_enable(void)
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
@ -372,8 +370,6 @@ int main(int argc, char **argv)
qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
qtest_add_func("stm32l4x5/usart/ack", test_ack);
qtest_add_func("stm32l4x5/usart/clock_enable", test_clock_enable);
ret = g_test_run();
return ret;
return g_test_run();
}

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@ -71,7 +71,6 @@ static void compute_default_paths(void)
static int is_intel_processor(void)
{
int result;
int ebx, ecx, edx;
/* Execute CPUID instruction with eax=0 (basic identification) */
@ -87,9 +86,7 @@ static int is_intel_processor(void)
* 0x49656e69 = "ineI"
* 0x6c65746e = "ntel"
*/
result = (ebx == 0x756e6547) && (edx == 0x49656e69) && (ecx == 0x6c65746e);
return result;
return (ebx == 0x756e6547) && (edx == 0x49656e69) && (ecx == 0x6c65746e);
}
static int is_rapl_enabled(void)