mirrors/qemu-project_qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2025-04-29 09:22:36 +08:00
Code Issues Packages Projects Releases Wiki Activity

i386/pc: Support cache topology in -machine for PC machine

Browse Source 
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.

Additionally, add the document of "-machine smp-cache" in
qemu-options.hx.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-5-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Zhao Liu 2025-01-10 22:51:14 +08:00 committed by Paolo Bonzini
parent 5ca9282d25
commit 90df2cac37
2 changed files with 33 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/i386/pc.c
View File

@ -1798,6 +1798,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
mc->smp_props.modules_supported = true;
mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
mc->default_ram_id = "pc.ram";
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;

30
qemu-options.hx
View File

@ -42,7 +42,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
" aux-ram-share=on|off allocate auxiliary guest RAM as shared (default: off)\n"
#endif
" memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n"
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n",
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n"
" smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel\n",
QEMU_ARCH_ALL)
SRST
``-machine [type=]name[,prop=value[,...]]``
@ -172,6 +173,33 @@ SRST
::
-machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512
``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel``
Define cache properties for SMP system.
``cache=cachename`` specifies the cache that the properties will be
applied on. This field is the combination of cache level and cache
type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction
cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache).
``topology=topologylevel`` sets the cache topology level. It accepts
CPU topology levels including ``core``, ``module``, ``cluster``, ``die``,
``socket``, ``book``, ``drawer`` and a special value ``default``. If
``default`` is set, then the cache topology will follow the architecture's
default cache topology model. If another topology level is set, the cache
will be shared at corresponding CPU topology level. For example,
``topology=core`` makes the cache shared by all threads within a core.
The omitting cache will default to using the ``default`` level.
The default cache topology model for an i386 PC machine is as follows:
``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``l3``
cache is per ``die``.
Example:
::
-machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core
ERST
DEF("M", HAS_ARG, QEMU_OPTION_M,